PV2 ⊧ yosys - Yosys Open SYnthesis Suiteconverts from Verilog to various formats and connects to other libraries

Framework for (Verilog) RTL synthesis tools.

Application domain/field

• RTL synthesis
• Verilog
• Circuit architecture design

Type of tool

Synthesis framework

Expected input

• Design
• Synthesis script

Format:

• Design: Verilog
• Synthesis script: ?

Internals

yosys supports several types of analyses, including:

• Converting Verilog to BLIF/EDIF/BTOR/SMT-LIB/etc.
• Synthesis algorithms for various application designs
• Mapping to ASIC standard cell libraries

Comments

License: ISC