PV2 ⊧ ADACsynthesises an approximate circuit from a given one and a set of constraints

Application domain/field

• Approximate computing (field aiming at reducing system resource demands, e.g. power demands)
• Circuit synthesis
• Circuit verification

Type of tool

Framework to design approximate arithmetic circuits

Expected input

• A golden combinational circuit in Verilog implementing the correct functionality
• Error metric (e.g. mean error, Hamming distance, etc.)
• Threshold on the error metric representing the maximal permissible error
• Time limit on the overall design process
• File specifying sizes of gates available to the design process

Format:

• Circuit in Verilog format
• Error metric, threshold on error metric and time limit seem to be specified in a configuration file (.conf)

Expected output

Approximate circuit satisfying the error threshold and with minimal estimated chip area (in gate-level Verilog format).

Internals

Implemented as a module of ABC. Uses Yosys, iprove, MiniSat.